Ethernet: Gigabit Media Independent Interface (GMII)

2025 Feb 25
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2347 words, 19 min read
Series: Ethernet
Tags: Embedded, Ethernet, Hardware, Network

When introducing Gigabit Ethernet, there was a problem adopting the existing MII. Simply increasing the clock speed another order of magnitude would bring it to 250 MHz and a period of 4 ns. This introduced two issues: First, the clock speed would be well in excess of those used by commodity memory buses of the time, making it difficult to implement. Second, the system synchronous design of the transmit path would make it impossible to control setup and hold timing.

So, in order to facilitate the new high speed protocol, a new xMII was introduced: the Gigabit Media Independent Interface (GMII), defined in Clause 35. This doubles the data bus width to a full byte, limiting the clock rate to a more modest 125 MHz, and switches the transmit path to a source-synchronous configuration. This interface is defined exclusively for Gigabit Ethernet but may occasionally crop up in 2.5G applications.

Given the high pin count and complexity when supporting 10/100/1000 operation, GMII is rarely seen as an inter-chip interface in modern designs. The externally defined RGMII (effectively a DDR version of GMII) or SGMII interfaces are more commonly seen. Despite this, these are still defined in context of GMII.

Note: The most recent version of the 802 standards are available from the IEEE Get program at no cost. It is highly advised that anyone working with Ethernet download a copy of 802.3 (Wired Ethernet).

Signaling (Clause 35.2) 🔗

GMII is defined by 24 individual signals, largely straightforward extensions from those used in MII. Each direction (transmit and receive) has eleven signals: a source-synchronous clock (RX_CLK/GTX_CLK), a valid/enable signal (RX_DV/TX_EN), an error signal (RX_ER/TX_ER), and an eight-bit data bus (RXD/TXD). The MII half-duplex signals, Carrier Sense (CRS) and Collision Detected (COL), are still present even though half-duplex was never widely supported on Gigabit.

GMII Signals

The transmit and receive paths are largely symmetric. RX_DV/TX_EN indicate when the medium is transmitting a packet and RX_ER/TX_ER indicate the presence of a special condition. Together, the combination of the valid/enable and error signals control the interpretation of the data bus with an equivalent encoding as MII:

`EN`	`ER`	Meaning	`RXD`/`TXD`
`0`	`0`	Bus Idle	(Do Not Care)
`0`	`1`	Control Word	Control Word
`1`	`0`	Transmit Data	Data Byte
`1`	`1`	Transmit Error	(Do Not Care)

Under normal operation, RX_ER/TX_ER is held low. Raising RX_DV/TX_EN is done to indicate when a packet is being sent (including during the preamble and SFD).

Packet Structure

Even though a standard preamble is 7 bytes of 0x55 followed by the SFD, as with MII, there is no guarantee you will receive the full preamble. It is advised that the MAC accept any number of 0x55, including zero, prior to the appearance of the SFD, 0xD5.

Clocking (Clause 35.5.2) 🔗

Both clocks in GMII are source-synchronous. The transmit clock is sourced by the MAC and the receive clock by the PHY. A standard clock 125 MHz (8 ns period) with a tolerance of 100 ppm and duty cycle between 35% and 75%. Setup and hold times are defined as 2.5 ns and 0.5 ns at the signal source, reducing to 2.0 ns and 0 ns at the receiver, indicating a maximum permissible mismatch of 500 ps when length matching.

Signal Timing

As with MII, the receive clock may be sourced from the local oscillator or the recovered clock from the peer and may be suppressed under Low Power Idle (LPI). Due to this, it may shift in frequency, phase, or disappear entirely based upon the link state. As such, it cannot be safely used as the reference for a PLL.

The MAC-provided transmit clock, GTX_CLK, may or may not be used for transmission on the media. In 1000Base-T, for example, part of autonegotiation process is to determine a master/slave relationship and the slave will use the recovered clock for transmission, maintaining a constant phase relationship between the two directions. This means that there will be transmit buffering within the PHY and may end up masking considerable clock error on minimum length packets while mysteriously failing on larger packets.

An example SDC would be:

# Requirements from 802.3
set clk_period 8
set txd_hold 0.5
set txd_setup 2.5
set rxd_hold 0.0
set rxd_setup 2.0

# Transmit Constraints
# TODO: Update source and division to match logic
create_generated_clock -name GTX_CLK [get_ports GTX_CLK] \
    -source [get_pins */GTX_CLK_GEN/C] -divide_by 1
set_output_delay -clock GTX_CLK -min -$txd_hold \
    [get_ports {TX_EN TX_ER TXD[*]}]
set_output_delay -clock GTX_CLK -max +$txd_setup \
    [get_ports {TX_EN TX_ER TXD[*]}]

# Receive Constraints
create_clock -name RX_CLK -period $clk_period [get_ports RX_CLK]
create_clock -name RX_CLK_virt -period $clk_period
set_input_delay -clock RX_CLK_virt -min $rxd_hold \
    [get_ports {RX_DV RX_ER RXD[*]}]
set_input_delay -clock RX_CLK_virt \
    -max [expr {$clk_period - $rxd_setup}] \
    [get_ports {RX_DV RX_ER RXD[*]}]

Data Errors (Clause 35.2.2.5, 35.2.2.9) 🔗

As with MII, encoding errors can be indicated by the use of RX_ER or TX_ER. When asserted during a packet (RX_DV/TX_EN are high), this indicates that an issue with that specific byte position. For example, on reception, the PHY detected a coding error and indicates the byte is invalid. Alternatively, on transmission, the MAC suffered a buffer underflow and needs to spoil the packet to ensure its peer will not mistakenly interpret it as a valid packet. The specific value of the data bus is undefined during a data error.

Example Packet Error

Control Sequences (Clause 35.2.2.4, 35.2.2.8) 🔗

As with MII, the error signal (RX_ER/TX_ER) can be used to indicate the presence of control sequences when the valid signal (RX_DV/TX_EN) are held low. The values are broadly similar to those in MII, simply zero extended, with the addition of two new values for the special handling of half-duplex in Gigabit.

Value	Transmit	Receive
`00`	Reserved	Normal Interframe
`01`	Assert LPI	Assert LPI
`0E`	Reserved	False Carrier
`0F`	Carrier Extend	Carrier Extend
`1F`	Carrier Extend Error	Carrier Extend Error

False Carrier (0E) typically indicates a coding error on the part of the remote peer (Clause 36.2.5.2.3). This can generally be ignored except for logging purposes but may indicate hardware malfunction.

Carrier Extend (0F) and Carrier Extend Error (1F) are used in half-duplex Gigabit operation to extend a packet to meet the minimums required by the extended slotTime. They are not normally part of full-duplex operation but may be introduced by 1000Base-X (e.g. fiber) and its derivatives (e.g. SGMII).

Tri-Mode Operation (Clause 35.3) 🔗

Tri-Mode (10/100/1000) operation is somewhat involved under GMII. As GMII is only defined for Gigabit operation, the bus is required to revert to MII when operating at reduced rate, including switching the transmit bus from GTX_CLK to TX_CLK and only sending one nibble at a time.

While operating at reduced rate, the high order bits (four through seven) and GTX_CLK becomes do-not-care. For power reduction and stability purposes, they should be driven to a known value (e.g. zero).

This means that a tri-mode PHY has 25 pins (the addition of TX_CLK) instead of the standard GMII set of 24. And both sets of constraints (MII and GMII) should be present for the transmit pins.

Link Configuration 🔗

The fundamental properties when configuring the interface, be it manually or through autonegotiation, are the following:

Link Speed. As the clocking structure changes between 10/100 and Gigabit, it is essential for the MAC to know which speed has been negotiated. Failure to do so will result in link failure.
Link Duplex. Half-duplex requires the implementation of CSMA/CD on the part of the MAC along with the Gigabit-specific complications. This is rarely supported on Gigabit and should be disabled in autonegotiation.
Energy Efficient Ethernet. EEE will result in the potential generation of LPI sequences by the peer, which may result in RX_CLK being halted. It also allows the local MAC to generate LPI sequences of its own and halt GTX_CLK to reduce power consumption.

These properties are not available in-band and need to be accessed through the management interface.

Note: Autonegotiation is required on 1000Base-T to determine the master/slave relationship. Even when disabled in the management interface, the autonegotiation process will still occur but with only one rate/duplex offered.

Crossover 🔗

Crossover in this context refers to connecting two devices of the same class (PHY or MAC) directly. For example, connecting the TX of one MAC directly to the RX of a second MAC without an intervening PHY, or using a pair of PHYs as a media converter.

As both sides of the link are source-synchronous and largely identical in their operation, direct crossover is broadly compatible. The only complication would be possible truncation of the preamble in a PHY-to-PHY crossover. There are no expected complications in a MAC-to-MAC crossover.

Energy Efficient Ethernet (Clause 35.4, 78) 🔗

As with 100Base-TX, the transmitters run continuously in Gigabit Ethernet, even when the link is idle. Energy Efficient Ethernet (EEE) is a mechanism by which the transmitter can be disabled during periods of extended inactivity, reducing power consumption. To maintain the link, the PHY will periodically enable its transmitter to send a refresh signal.

First, EEE support needs to be negotiated with the peer. On some PHYs, this is enabled by default. On others, some form of configuration is required. This is normally handled through the Clause 45 register sets MMD3 and MMD7.

When the peer signals it is entering Low Power Idle (LPI), the local PHY will report this to the MAC by signalling Assert LPI, holding RX_DV low, RX_ER high, and 01 on RXD. Once the PHY has indicated this condition for at least nine clock cycles, and clock stop has been enabled in the management interface, it may halt RX_CLK until the peer leaves LPI while leaving RXD in Assert LPI. Upon leaving LPI, the PHY will hold Assert LPI for at least one cycle before transitioning to normal idle.

LPI Receive Timing

When the local MAC is idle, it may request the PHY enter LPI in a similar manner: It pulls TX_EN low, TX_ER high, and loads 01 onto TXD. However, when it wishes to resume transmission, it cannot do so immediately upon releasing Assert LPI. The peer needs time to synchronize its clock recovery and descrambler. The minimum required time is specified in Clause 78 as T_{w_sys_tx}, which is provided for each PHY in Table 78-4. For the PHYs covered by Clause 35 GMII, these times are:

For 1000Base-KX, this is 13.26 μs (1657.5 clock cycles).
For 1000Base-T, this is 16.5 μs (2062.5 clock cycles).
For 1000Base-T1, this is 10.8 μs (1350 clock cycles).

Unlike MII, the transmit clock is under the control of the MAC, so it has the ability to halt the transmit clock. If clock stop has been enabled in the management interface, the MAC is allowed to halt GTX_CLK after clocking at least nine cycles of Assert LPI. The MAC is required to hold Assert LPI while the clock is stopped and while it is recommended this continue for at least one cycle upon resuming, it is not required.

LPI Transmit Timing

Failure to meet these timing requirements may result in data loss as the peer may not have been able to complete synchronization.

Half-Duplex (Clause 4.2.3.2, 35.2.2) 🔗

The specification for 1000Base-T includes half-duplex operation (Clause 41). To my knowledge, Gigabit hubs were never commercially available and, as a result, many pieces of Gigabit hardware do not include support for half-duplex operation. As such, it is best to disable half-duplex operation in the autonegotiation register set.

Half-Duplex operation in Gigabit is broadly similar to that in 10/100 with one notable exception. As the duration of a minimum length frame at these speeds is less than the round-trip time at the maximum segment length, the slotTime was increased from 512 bits (64 bytes) to 4096 bits (512 bytes). This means the MAC must hold the media for at least that long in order to detect collisions.

Instead of increasing the minimum packet size, GMII allows one to hold the carrier beyond the end of a frame by using the Carrier Extend condition (0F) listed previously. This acts like an IPG between packets while maintaining the carrier. To avoid simply wasting this time, after the normal 96 bits (12 bytes) of IPG and, if still within the initial slotTime, the MAC may continue transmitting packets.

While half-duplex Gigabit may be a historical curiosity, Carrier Extend does make an appearance in 1000Base-X (e.g. fiber and SGMII). Even in full-duplex operation, a couple cycles may appear at the end of each frame due to the nature of the encoding.

Ten Bit Interface (Clause 35.3, 36.3) 🔗

1000Base-X (and its derivatives) encodes the packet stream using 8b10b encoding, where every byte (8b) is encoded with ten bits (10b). The specifics of this encoding will be covered in the article on 1000Base-X; however, GMII includes a provision to carry the PCS encoding directly. This mode is known as the Ten Bit Interface (TBI), covered by Clause 36.3.

GMII covers the mapping between its signals and TBI in Clause 35.3. Under TBI, RXD[7:0] and TXD[7:0] map to the low order eight bytes directly, while RX_DV/TX_EN map to the ninth bit and RX_ER/TX_ER map to the tenth. This is merely a pin assignment; the PCS encoding is not equivalent to that described in previous sections.

As 1000Base-T does not use this encoding, it makes little sense when communicating with a traditional PHY where it is rarely supported (e.g. Marvell Alaska 88E1111). This encoding is used with 1000Base-X (e.g. fiber), where one is more likely to use the high-speed transceivers built into the processor or FPGA instead of an external PHY.